[all-commits] [llvm/llvm-project] c44dca: MachineVerifier: Reject extra non-register operand...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c44dca15a4297eef3b9319a5e24f85267a099642
      https://github.com/llvm/llvm-project/commit/c44dca15a4297eef3b9319a5e24f85267a099642
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2023-11-30 (Thu, 30 Nov 2023)

  Changed paths:
    M llvm/lib/CodeGen/MIRParser/MIParser.cpp
    M llvm/lib/CodeGen/MachineInstr.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/Target/MSP430/MSP430RegisterInfo.cpp
    R llvm/test/CodeGen/MIR/AMDGPU/extra-imm-operand.mir
    R llvm/test/CodeGen/MIR/AMDGPU/extra-reg-operand.mir
    A llvm/test/MachineVerifier/verify-implicit-def.mir

  Log Message:
  -----------
  MachineVerifier: Reject extra non-register operands on instructions (#73758)

We were allowing extra immediate arguments, and only bothering to check
if registers were implicit or not.

Also consolidate extra operand checks in verifier, to make this
testable. We had 3 different places checking if you were trying to build
an instruction with more operands than allowed by the definition. We had
an assertion in addOperand, a direct check in the MIRParser to avoid the
assertion, and the machine verifier checks. Remove the assert and parser
check so the verifier can provide a consistent verification experience,
which will also handle instructions modified in place.