[all-commits] [llvm/llvm-project] e3021b: [RISCV] Add RISCVISD::SLLW to computeKnownBitsForT...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e3021bdecde584c48bfd43ce4991ab7762751f09
      https://github.com/llvm/llvm-project/commit/e3021bdecde584c48bfd43ce4991ab7762751f09
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-29 (Wed, 29 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  Log Message:
  -----------
  [RISCV] Add RISCVISD::SLLW to computeKnownBitsForTargetNode.

Found while investigating whether we still need to stop DAG combiner
from turning (i64 (sext (i32 X))) into zext when i32 is known non
negative.

No test case because I still need to find fixes for some other issues
before I can remove the code from DAGCombiner.