[all-commits] [llvm/llvm-project] f35c0f: [RISCV] Refine pattern (select_cc seteq (and x, C)...

[Yeting Kuo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f35c0f2f232a0b298a35bfb0047bf8a00b107bf0
      https://github.com/llvm/llvm-project/commit/f35c0f2f232a0b298a35bfb0047bf8a00b107bf0
  Author: Yeting Kuo <46629943+yetingk at users.noreply.github.com>
  Date:   2023-11-29 (Wed, 29 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/condops.ll

  Log Message:
  -----------
  [RISCV] Refine pattern (select_cc seteq (and x, C), 0, 0, A) with Zbs. (#73746)

PR #72978 disabled transformation (select_cc seteq (and x, C), 0, 0, A)
-> (and (sra(shl x)), A) for better Zicond codegen. It still enables the
combine when C is not fit into 12-bits. This patch disables the combine
when Zbs enabled.