[all-commits] [llvm/llvm-project] 02cbae: [RISCV] Work on subreg for insert_vector_elt when ...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 02cbae4fe0683c90ccd544d0be7fa82732a502e8
      https://github.com/llvm/llvm-project/commit/02cbae4fe0683c90ccd544d0be7fa82732a502e8
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-11-28 (Tue, 28 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

  Log Message:
  -----------
  [RISCV] Work on subreg for insert_vector_elt when vlen is known (#72666) (#73680)

If we have a constant index and a known vlen, then we can identify which
registers out of a register group is being accessed. Given this, we can
reuse the (slightly generalized) existing handling for working on
sub-register groups. This results in all constant index extracts with
known vlen becoming m1 operations.

One bit of weirdness to highlight and explain: the existing code uses
the VL from the original vector type, not the inner vector type. This is
correct because the inner register group must be smaller than the
original (possibly fixed length) vector type. Overall, this seems to a
reasonable codegen tradeoff as it biases us towards immediate AVLs,
which avoids needing the vsetvli form which clobbers a GPR for no real
purpose. The downside is that for large fixed length vectors, we end up
materializing an immediate in register for little value. We should
probably generalize this idea and try to optimize the large fixed length
vector case, but that can be done in separate work.