[all-commits] [llvm/llvm-project] f3a9db: [RISCV] Split build_vector into vreg sized pieces ...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f3a9dbe7fcabb10d81a56d3757fb1b32fa37972e
      https://github.com/llvm/llvm-project/commit/f3a9dbe7fcabb10d81a56d3757fb1b32fa37972e
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-11-28 (Tue, 28 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

  Log Message:
  -----------
  [RISCV] Split build_vector into vreg sized pieces when exact VLEN is known (#73606)

If we have a high LMUL build_vector and a known exact VLEN, we can
decompose the build_vector into one build_vector per register in the
register group. Doing so requires exact knowledge of which elements
correspond to each register in the register group, and thus an exact
VLEN must be known.

Since we no longer have operations which are linear (or worse) in LMUL,
this also allows us to lower all build_vectors without resorting to
going through the stack.