[all-commits] [llvm/llvm-project] 21b30e: [NFC][TLI] Improve tests for ArmPL and SLEEF Intri...

[Paschalis Mpeis via All-commits]

  Branch: refs/heads/users/paschalis-mpeis/replace-with-veclip-scalable-vec
  Home:   https://github.com/llvm/llvm-project
  Commit: 21b30e18814016dc61b1a1ed87609e53454e3553
      https://github.com/llvm/llvm-project/commit/21b30e18814016dc61b1a1ed87609e53454e3553
  Author: Paschalis Mpeis <Paschalis.Mpeis at arm.com>
  Date:   2023-11-24 (Fri, 24 Nov 2023)

  Changed paths:
    M llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll
    M llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sleef-intrinsic-calls-aarch64.ll

  Log Message:
  -----------
  [NFC][TLI] Improve tests for ArmPL and SLEEF Intrinsics.

Auto-generate test `armpl-intrinsics.ll`, and use active lane mask to
have shorter `shufflevector` check lines.

Update scripts now add `@llvm.compiler.used` instead of using the regex:
`@[[LLVM_COMPILER_USED:[a-zA-Z0-9_$"\\.-]+]]`


  Commit: cace1ec7346d3dfee9fcc5d67d79bce989b207d1
      https://github.com/llvm/llvm-project/commit/cace1ec7346d3dfee9fcc5d67d79bce989b207d1
  Author: Paschalis Mpeis <Paschalis.Mpeis at arm.com>
  Date:   2023-11-27 (Mon, 27 Nov 2023)

  Changed paths:
    M llvm/test/Transforms/LoopVectorize/AArch64/armpl-intrinsics.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sleef-intrinsic-calls-aarch64.ll

  Log Message:
  -----------
  Add `simplifycfg` pass and `noalias` to ensure tail folding.

`noalias` attribute was added only to the `%in.ptr` parameter of the
ArmPL Intrinsics.


  Commit: 6f797921e23fe9a4500222e69ebd75aa7ba53ec1
      https://github.com/llvm/llvm-project/commit/6f797921e23fe9a4500222e69ebd75aa7ba53ec1
  Author: Paschalis Mpeis <Paschalis.Mpeis at arm.com>
  Date:   2023-11-28 (Tue, 28 Nov 2023)

  Changed paths:
    M llvm/lib/Analysis/VFABIDemangling.cpp
    M llvm/lib/CodeGen/ReplaceWithVeclib.cpp
    M llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-armpl.ll
    M llvm/test/CodeGen/AArch64/replace-intrinsics-with-veclib-sleef-scalable.ll

  Log Message:
  -----------
  [TLI] Pass replace-with-veclib works with Scalable Vectors.

The pass uses the Masked variant of TLI method when the Intrinsic
operates on Scalable Vectors and it fails to find a non-Masked variant.


Compare: https://github.com/llvm/llvm-project/compare/21b30e188140%5E...6f797921e23f