[all-commits] [llvm/llvm-project] cf17a2: [RISCV] Use subreg extract for extract_vector_elt ...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cf17a24a4b47dde8b0222a3e641d55fe8f36a083
      https://github.com/llvm/llvm-project/commit/cf17a24a4b47dde8b0222a3e641d55fe8f36a083
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-11-27 (Mon, 27 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll

  Log Message:
  -----------
  [RISCV] Use subreg extract for extract_vector_elt when vlen is known (#72666)

This is the first in a planned patch series to teach our vector lowering
how to exploit register boundaries in LMUL>1 types when VLEN is known to
be an exact constant. This corresponds to code compiled by clang with
the -mrvv-vector-bits=zvl option.

For extract_vector_elt, if we have a constant index and a known vlen,
then we can identify which register out of a register group is being
accessed. Given this, we can do a sub-register extract for that
register, and then shift any remaining index.

This results in all constant index extracts becoming m1 operations, and
thus eliminates the complexity concern for explode-vector idioms at high
lmul.