[all-commits] [llvm/llvm-project] 5f31db: [RISCV] Add register bank and instruction selectio...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5f31dbd18d24f0084363891139edf4fe71081eed
      https://github.com/llvm/llvm-project/commit/5f31dbd18d24f0084363891139edf4fe71081eed
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-27 (Mon, 27 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-select-rv64.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv32.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/fp-select-rv64.mir

  Log Message:
  -----------
  [RISCV] Add register bank and instruction selection support for FP G_SELECT. (#72726)

Try to pick the FP register bank based on surrounding use/defs. Code is
basically copied from AArch64.

Need legalizer changes to make this more useful. Right now we're stuck
with only being able to FP select types less than or equal to XLen.