[all-commits] [llvm/llvm-project] b6d167: [LivePhysRegs] Add callee-saved regs from MFI in a...

[Florian Hahn via All-commits]

  Branch: refs/heads/users/fhahn/live-phys-regs-arm-callee-saved-mfi
  Home:   https://github.com/llvm/llvm-project
  Commit: b6d1671632748d222e4ed4e2fb2db34b0846714d
      https://github.com/llvm/llvm-project/commit/b6d1671632748d222e4ed4e2fb2db34b0846714d
  Author: Florian Hahn <flo at fhahn.com>
  Date:   2023-11-27 (Mon, 27 Nov 2023)

  Changed paths:
    M llvm/lib/CodeGen/LivePhysRegs.cpp
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/ctlz-non-zeros.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/invariant-qreg.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-mov.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp-reordered.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-vcmp.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/livereg-no-loop-def.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/massive.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-cond-iter-count.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiblock-massive.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-reduct-livein-arg.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-invariant.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/remove-elem-moves.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/safe-retaining.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/size-limit.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/subreg-liveness.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredicated-max.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unsafe-retaining.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir
    M llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
    M llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
    M llvm/test/CodeGen/Thumb2/outlined-fn-may-clobber-lr-in-caller.ll

  Log Message:
  -----------
  [LivePhysRegs] Add callee-saved regs from MFI in addLiveOutsNoPristines.

Some callee-saved registers may be implicitly used by a
return/terminator instruction in return blocks, e.g. LR on ARM. When
computing the live-ins for a return block, add all callee-saved
registers from the current frame info. This is in line with how PEI
updates liveness in updateLiveness.

This fixes a mis-compile in outlined-fn-may-clobber-lr-in-caller.ll
where the machine-outliner previously introduced BLs that clobbered LR
which in turn is used by the tail call return.

Almost all est changes are in MTE, where we have a sequence of
    tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc

With this patch, the exit block is assumed to use LR implicitly, even
though POP_RET restores it to PC and doesn't use LR. I am not sure if
there's a way around that without more accurate modeling of uses of LR.

It would be great to teach the machine-verifier to check liveness of LR
on ARM, but I couldn't find an appropriate hook to teach it about which
instructions implicitly use LR.