[all-commits] [llvm/llvm-project] 672752: [X86] X86DAGToDAGISel - attempt to merge XMM/YMM l...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 67275263b3b781a55ec4f297b5f42ffd783349ec
      https://github.com/llvm/llvm-project/commit/67275263b3b781a55ec4f297b5f42ffd783349ec
  Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
  Date:   2023-11-23 (Thu, 23 Nov 2023)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
    M llvm/test/CodeGen/X86/avx512-regcall-Mask.ll
    M llvm/test/CodeGen/X86/bfloat.ll
    M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
    M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
    M llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
    M llvm/test/CodeGen/X86/constant-pool-sharing.ll
    M llvm/test/CodeGen/X86/insert-into-constant-vector.ll
    M llvm/test/CodeGen/X86/midpoint-int-vec-512.ll
    M llvm/test/CodeGen/X86/pr57340.ll
    M llvm/test/CodeGen/X86/splat-for-size.ll
    M llvm/test/CodeGen/X86/subvector-broadcast.ll
    M llvm/test/CodeGen/X86/vec_fabs.ll
    M llvm/test/CodeGen/X86/vec_int_to_fp.ll
    M llvm/test/CodeGen/X86/vector-fshl-256.ll
    M llvm/test/CodeGen/X86/vector-fshl-512.ll
    M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-256.ll
    M llvm/test/CodeGen/X86/vector-fshr-512.ll
    M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-sext.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
    M llvm/test/CodeGen/X86/viabs.ll
    M llvm/test/CodeGen/X86/vselect-avx.ll
    M llvm/test/CodeGen/X86/x86-interleaved-access.ll
    M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
    M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll

  Log Message:
  -----------
  [X86] X86DAGToDAGISel - attempt to merge XMM/YMM loads with YMM/ZMM loads of the same ptr (#73126)

If we are loading the same ptr at different vector widths, then reuse the larger load and just extract the low subvector.

Unlike the equivalent VBROADCAST_LOAD/SUBV_BROADCAST_LOAD folds which can occur in DAG, we have to wait until DAGISel otherwise we can hit infinite loops if constant folding recreates the original constant value.

This is mainly useful for better constant sharing.