[all-commits] [llvm/llvm-project] 147c5d: [AArch64] Allow LDR merge with same destination re...

[Zhaoxuan Jiang via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 147c5d6686b935ecd93f8fa0e2dcf38deb593890
      https://github.com/llvm/llvm-project/commit/147c5d6686b935ecd93f8fa0e2dcf38deb593890
  Author: Zhaoxuan Jiang <jiangzhaoxuan94 at gmail.com>
  Date:   2023-11-23 (Thu, 23 Nov 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
    M llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
    M llvm/test/CodeGen/AArch64/fexplog.ll
    M llvm/test/CodeGen/AArch64/fpow.ll
    M llvm/test/CodeGen/AArch64/frem.ll
    M llvm/test/CodeGen/AArch64/fsincos.ll
    M llvm/test/CodeGen/AArch64/ldrpre-ldr-merge.mir
    M llvm/test/CodeGen/AArch64/neon-dotreduce.ll
    M llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp128.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add.ll

  Log Message:
  -----------
  [AArch64] Allow LDR merge with same destination register by renaming (#71908)

The patch is based on a reverted patch:
https://reviews.llvm.org/D103597. It was trying to rename registers
before alias check, which is not safe and causes miscompiles. This patch
does 2 things:

1. Do the renaming with necessary checks passed, including alias check.
2. Rename the register for the instructions between the pairs and
combine the second load into the first. By doing so we can just check
the renamability between the pairs and avoid scanning unknown amount of
instructions before/after the pairs.

Necessary refactoring has been made in order to reuse as much code
possible with STR renaming.