[all-commits] [llvm/llvm-project] dff97c: [mlir][ArmSME] Move ArmSME -> intrinsics lowerings...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dff97c1e4c30183dbd056c6a648b17f2cc87c972
      https://github.com/llvm/llvm-project/commit/dff97c1e4c30183dbd056c6a648b17f2cc87c972
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2023-11-22 (Wed, 22 Nov 2023)

  Changed paths:
    A mlir/include/mlir/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.h
    M mlir/include/mlir/Conversion/Passes.h
    M mlir/include/mlir/Conversion/Passes.td
    M mlir/include/mlir/Dialect/ArmSME/Transforms/Transforms.h
    A mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp
    A mlir/lib/Conversion/ArmSMEToLLVM/CMakeLists.txt
    M mlir/lib/Conversion/CMakeLists.txt
    M mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.cpp
    M mlir/lib/Dialect/ArmSME/Transforms/CMakeLists.txt
    R mlir/lib/Dialect/ArmSME/Transforms/LegalizeForLLVMExport.cpp
    M mlir/test/Dialect/ArmSME/arm-sme-to-llvm-casts.mlir
    M mlir/test/Dialect/ArmSME/arm-sme-to-llvm.mlir
    M mlir/test/Dialect/ArmSME/enable-arm-za.mlir
    M mlir/test/Dialect/ArmSME/tile-zero-masks.mlir
    M mlir/test/Dialect/ArmSME/vector-ops-to-llvm.mlir
    M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/fill-2d.mlir
    M mlir/test/Integration/Dialect/Linalg/CPU/ArmSME/matmul-transpose-a.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/load-store-128-bit-tile.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-load-vertical.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f32.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-f64.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-read-2d.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transfer-write-2d.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-transpose.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/tile_fill.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-load-store.mlir
    M mlir/test/Integration/Dialect/Vector/CPU/ArmSME/vector-ops.mlir

  Log Message:
  -----------
  [mlir][ArmSME] Move ArmSME -> intrinsics lowerings to `convert-arm-sme-to-llvm` pass (#72890)

This gives more flexibility with when these lowerings are performed,
without also lowering unrelated vector ops.

This is a NFC (other than adding a new `-convert-arm-sme-to-llvm` pass)