[all-commits] [llvm/llvm-project] a756a6: [TargetLowering][RISCV] Introduce shouldFoldSelect...

[Yeting Kuo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a756a6b97e44d0c446111a3a34afdee0dacadfe7
      https://github.com/llvm/llvm-project/commit/a756a6b97e44d0c446111a3a34afdee0dacadfe7
  Author: Yeting Kuo <46629943+yetingk at users.noreply.github.com>
  Date:   2023-11-22 (Wed, 22 Nov 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/condops.ll
    M llvm/test/CodeGen/RISCV/select.ll

  Log Message:
  -----------
  [TargetLowering][RISCV] Introduce shouldFoldSelectWithSingleBitTest and RISC-V implement. (#72978)

DAGCombiner folds (select_cc seteq (and x, y), 0, 0, A) to (and (sra
(shl x)) A) where y has a single bit set. Previously, DAGCombiner relies
on `shouldAvoidTransformToShift` to decide when to do the combine, but
`shouldAvoidTransformToShift` is only about shift cost. This patch
introuduces a specific hook to decide when to do the combine and disable
the combine when Zicond enabled and AndMask <= 1024.