[all-commits] [llvm/llvm-project] 9166cd: [RISCV] DAG combine (mul (add x, 1), y) -> vmadd (...

[Liao Chunyu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9166cd2a71ba81d2c9c68f80371b1397943a813b
      https://github.com/llvm/llvm-project/commit/9166cd2a71ba81d2c9c68f80371b1397943a813b
  Author: Liao Chunyu <chunyu at iscas.ac.cn>
  Date:   2023-11-21 (Tue, 21 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll

  Log Message:
  -----------
  [RISCV] DAG combine (mul (add x, 1), y) -> vmadd (#71495)

vmadd: (mul (add x, 1), y) -> (add (mul x, y), y)
           (mul x, add (y, 1)) -> (add x, (mul x, y))
    vnmsub: (mul (sub 1, x), y) -> (sub y, (mul x, y))
            (mul x, (sub 1, y)) -> (sub x, (mul x, y))
    
    Comparison with gcc:
    vmadd: https://gcc.godbolt.org/z/xjePx87Y7
    vnsub: https://gcc.godbolt.org/z/b17zG7nT1