[all-commits] [llvm/llvm-project] 4028dd: [InstSimplify] Fold converted urem to 0 if there's...

[Graham Hunter via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4028dd2e93fa1697b68339b04b89f5ddbf7f9aea
      https://github.com/llvm/llvm-project/commit/4028dd2e93fa1697b68339b04b89f5ddbf7f9aea
  Author: Graham Hunter <graham.hunter at arm.com>
  Date:   2023-11-20 (Mon, 20 Nov 2023)

  Changed paths:
    M llvm/lib/Analysis/InstructionSimplify.cpp
    M llvm/test/Transforms/InstSimplify/po2-shift-add-and-to-zero.ll

  Log Message:
  -----------
  [InstSimplify] Fold converted urem to 0 if there's no overlapping bits (#71528)

When folding urem instructions we can end up not recognizing that
the output will always be 0 due to Value*s being different, despite
generating the same data (in this case, 2 different calls to vscale).

This patch recognizes the (x << N) & (add (x << M), -1) pattern that
instcombine replaces urem with after the two vscale calls have been
reduced to one via CSE, then replaces with 0 when x is a power of 2
and N >= M.