[all-commits] [llvm/llvm-project] 95d584: [InstCombine] Convert or concat to fshl if opposit...

[HaohaiWen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 95d584c6ac5b518a66992293b4ff63fc05a81685
      https://github.com/llvm/llvm-project/commit/95d584c6ac5b518a66992293b4ff63fc05a81685
  Author: HaohaiWen <haohai.wen at intel.com>
  Date:   2023-11-20 (Mon, 20 Nov 2023)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
    M llvm/test/Transforms/InstCombine/funnel.ll

  Log Message:
  -----------
  [InstCombine] Convert or concat to fshl if opposite or concat exists (#68502)

If there are two 'or' instructions concat variables in opposite order
and the first 'or' dominates the second one, the second 'or' can be
optimized to fshl to rotate shift first 'or'. This can eliminate an shl
and expose more optimization opportunity for bswap/bitreverse.