[all-commits] [llvm/llvm-project] 0765f6: [RISCV] Use correct register class for Z[df]inx in...

[Nemanja Ivanovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0765f6451ff964c4e209133e4ddef00a52dc9e7f
      https://github.com/llvm/llvm-project/commit/0765f6451ff964c4e209133e4ddef00a52dc9e7f
  Author: Nemanja Ivanovic <nemanja.i.ibm at gmail.com>
  Date:   2023-11-17 (Fri, 17 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll

  Log Message:
  -----------
  [RISCV] Use correct register class for Z[df]inx inline asm (#71872)

Allocate a register of the correct register class for inline asm
constraint "r" when used for FP values with -Zfinx/-Zdinx.

---------

Co-authored-by: Nemanja Ivanovic <nemanja at synopsys.com>