[all-commits] [llvm/llvm-project] 4eaf98: [RISCV] Add test cases for (not (sll -1, X)) for Z...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4eaf986be49daf8985e1fc32a658a951bb12ba3b
      https://github.com/llvm/llvm-project/commit/4eaf986be49daf8985e1fc32a658a951bb12ba3b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-16 (Thu, 16 Nov 2023)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv32zbs.ll
    M llvm/test/CodeGen/RISCV/rv64zbs.ll

  Log Message:
  -----------
  [RISCV] Add test cases for (not (sll -1, X)) for Zbs. NFC

We can use (ADDI (BSET X0, X), -1).


  Commit: 927f6f185898e9f8559c49de343f70789dd23e4a
      https://github.com/llvm/llvm-project/commit/927f6f185898e9f8559c49de343f70789dd23e4a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-16 (Thu, 16 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/rv32zbs.ll
    M llvm/test/CodeGen/RISCV/rv64zbs.ll

  Log Message:
  -----------
  [RISCV] Use bset+addi for (not (sll -1, X)).

This is an alternative to #71420 that handles i32 on RV64 safely
by pre-promoting the pattern in DAG combine.


Compare: https://github.com/llvm/llvm-project/compare/f8e8530f7377...927f6f185898