[all-commits] [llvm/llvm-project] 667ba7: [AMDGPU] Fix GCNRewritePartialRegUses pass: vector...

[Valery Pykhtin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 667ba7f8f31f7439e204c4efbd2aa576cd17273f
      https://github.com/llvm/llvm-project/commit/667ba7f8f31f7439e204c4efbd2aa576cd17273f
  Author: Valery Pykhtin <valery.pykhtin at gmail.com>
  Date:   2023-11-16 (Thu, 16 Nov 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
    M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
    M llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir

  Log Message:
  -----------
  [AMDGPU] Fix GCNRewritePartialRegUses pass: vector regclass is selected instead of scalar. (#69957)

For the following testcase:

undef %1.sub1:sgpr_96 = COPY undef %0:sgpr_32
%3:vgpr_32 = V_LSHL_ADD_U32_e64 %1.sub1:sgpr_96, ...

GCNRewritePartialRegUses produced:

%4:vgpr_32 = COPY undef %1:sgpr_32
dead %2:vgpr_32 = V_LSHL_ADD_U32_e64 %4, ...

Register class for %4 is incorrect: there should be sgpr_32 instead of
vgpr_32 because the original %1 had scalar regclass. This patch fixes
that.

Note that GCNRewritePartialRegUses pass isn't enabled by default yet.