[all-commits] [llvm/llvm-project] ac4868: [RISCV] Split regalloc between RVV and other (#72096)

[Piyou Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ac4868ea3c495baf5cbcb729e03f95b4425420dc
      https://github.com/llvm/llvm-project/commit/ac4868ea3c495baf5cbcb729e03f95b4425420dc
  Author: Piyou Chen <piyou.chen at sifive.com>
  Date:   2023-11-16 (Thu, 16 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

  Log Message:
  -----------
  [RISCV] Split regalloc between RVV and other (#72096)

Enable this flow by -riscv-split-regalloc=1 (default disable), and could
designate specific allocator to RVV by
-riscv-rvv-regalloc=<fast|basic|greedy>

It uses the RegClass filter function to decide which regclass need to be
processed.

This patch is pre-requirement for supporting PostRA vsetvl insertion
pass.