[all-commits] [llvm/llvm-project] ce7fd4: [AMDGPU] RA inserted scalar instructions can be at...

[Christudasan Devadasan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ce7fd498ed91344c23f0864bbd5b84d65eaae3ef
      https://github.com/llvm/llvm-project/commit/ce7fd498ed91344c23f0864bbd5b84d65eaae3ef
  Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
  Date:   2023-11-16 (Thu, 16 Nov 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineBasicBlock.h
    M llvm/include/llvm/CodeGen/TargetInstrInfo.h
    M llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp
    M llvm/lib/CodeGen/InlineSpiller.cpp
    M llvm/lib/CodeGen/MachineBasicBlock.cpp
    M llvm/lib/CodeGen/SplitKit.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.h
    M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
    M llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir

  Log Message:
  -----------
  [AMDGPU] RA inserted scalar instructions can be at the BB top (#72140)

We adjust the insertion point at the BB top for spills/copies during RA
to ensure they are placed after the exec restore instructions required
for the divergent control flow execution. This is, however, required
only for the vector operations. The insertions for scalar registers can
still go to the BB top.