[all-commits] [llvm/llvm-project] 71a710: [RISCV][MC] MC layer support for xcvmem and xcvelw...

[Liao Chunyu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 71a7108ee91a522251ff37638e26158570c1e2a5
      https://github.com/llvm/llvm-project/commit/71a7108ee91a522251ff37638e26158570c1e2a5
  Author: LiaoChunyu <chunyu at iscas.ac.cn>
  Date:   2023-11-16 (Thu, 16 Nov 2023)

  Changed paths:
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/docs/RISCVUsage.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/test/MC/RISCV/attribute-arch.s
    A llvm/test/MC/RISCV/corev/XCVelw-invalid.s
    A llvm/test/MC/RISCV/corev/XCVelw-valid.s
    A llvm/test/MC/RISCV/corev/XCVmem-invalid.s
    A llvm/test/MC/RISCV/corev/XCVmem-valid.s
    M llvm/unittests/Support/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV][MC] MC layer support for xcvmem and xcvelw extensions

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Several other extensions have been merged.
Spec:
https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst
Contributors: @CharKeaney, @jeremybennett, @lewis-revill, Nandni Jamnadas, @PaoloS, @simoncook, @xmj, @realqhc, @melonedo, @adeelahmad81299

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158824