[all-commits] [llvm/llvm-project] f219e0: [RISCV] Use TypeSize in places where needed for Re...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f219e03f3c9bea4220925838c3d57d5a993d4d7a
      https://github.com/llvm/llvm-project/commit/f219e03f3c9bea4220925838c3d57d5a993d4d7a
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-11-15 (Wed, 15 Nov 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/RegisterBankInfo.h
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/CodeGen/RegisterBankInfo.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h

  Log Message:
  -----------
  [RISCV] Use TypeSize in places where needed for RegBankSelection

This is a precommit for #71514 to use TypeSize instead of unsigned to
avoid crashes when scalable vectors are used.


  Commit: dbd884cd3da720b0adbd52142f1426745ab9d181
      https://github.com/llvm/llvm-project/commit/dbd884cd3da720b0adbd52142f1426745ab9d181
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-11-15 (Wed, 15 Nov 2023)

  Changed paths:
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/vec-args-ret.mir

  Log Message:
  -----------
  [RISCV][GISEL] Add vector RegisterBanks and vector support in getRegBankFromRegClass

Vector Register banks are created for the various register vector
register groupings. getRegBankFromRegClass is implemented to go from
vector TargetRegisterClass to the corresponding vector RegisterBank.


Compare: https://github.com/llvm/llvm-project/compare/170810fca6ee...dbd884cd3da7