[all-commits] [llvm/llvm-project] 725e59: [RISCV][GISEL] Add support for scalable vector typ...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 725e599637d9764b60aa09d5d4d3266b6dfc4e60
      https://github.com/llvm/llvm-project/commit/725e599637d9764b60aa09d5d4d3266b6dfc4e60
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-11-15 (Wed, 15 Nov 2023)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    M llvm/lib/CodeGen/MachineVerifier.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret-bf16-err.ll
    A llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret-f16-err.ll
    A llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/vec-ret.ll

  Log Message:
  -----------
  [RISCV][GISEL] Add support for scalable vector types in lowerReturnVal (#71587)

Scalable vector types from LLVM IR are lowered into physical vector
registers in MIR based on calling convention for return instructions.