[all-commits] [llvm/llvm-project] 05f70f: [RISCV] Add IsSignExtendingOpW to LR_W and SC_W as...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 05f70f7987f6bb34393b6ea0781c1060234a22ea
      https://github.com/llvm/llvm-project/commit/05f70f7987f6bb34393b6ea0781c1060234a22ea
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-15 (Wed, 15 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoA.td

  Log Message:
  -----------
  [RISCV] Add IsSignExtendingOpW to LR_W and SC_W as well. NFC

These instructions don't exist in the CodeGen pipeline early
enough for RISCVOptWInstrs to see them, but they still have the property.