[all-commits] [llvm/llvm-project] 95dd0b: AMDGPU/SILowerI1Copies process phi incomings in sp...

[petar-avramovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 95dd0b04d270fe3262e2494bfb9033d8ca07470a
      https://github.com/llvm/llvm-project/commit/95dd0b04d270fe3262e2494bfb9033d8ca07470a
  Author: petar-avramovic <56677889+petar-avramovic at users.noreply.github.com>
  Date:   2023-11-15 (Wed, 15 Nov 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
    A llvm/test/CodeGen/AMDGPU/si-lower-i1-copies-order-of-phi-incomings.mir

  Log Message:
  -----------
  AMDGPU/SILowerI1Copies process phi incomings in specific order (#72375)

When merging lane masks, value from block that is always visited first
(PrevReg in buildMergeLaneMasks) needs to exist because we do on-the-fly
constant folding. For PrevReg to exist, basic block that should contain
PrevReg definition must be processed first. Sort the incomings such that
incoming values that dominate other incoming values are processed first.

Sorting of phi incomings makes no changes for phis created by SDAG
because SDAG adds phi incomings as it selects basic blocks in reversed
post order traversal.

This change is required by upcoming lane mask merging implementation
for GlobalISel that leaves phi incomings as they are in IR.