[all-commits] [llvm/llvm-project] 51c351: [X86][MC] Support decoding of EGPR for APX (#72102)

[Shengchen Kan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 51c351f49ed1e1406543fcadc7f6d3a4272e74bd
      https://github.com/llvm/llvm-project/commit/51c351f49ed1e1406543fcadc7f6d3a4272e74bd
  Author: Shengchen Kan <shengchen.kan at intel.com>
  Date:   2023-11-15 (Wed, 15 Nov 2023)

  Changed paths:
    M llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
    M llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
    A llvm/test/MC/Disassembler/X86/apx/evex-format.txt
    A llvm/test/MC/Disassembler/X86/apx/rex2-bit.txt
    A llvm/test/MC/Disassembler/X86/apx/rex2-format.txt
    R llvm/test/MC/Disassembler/X86/invalid-EVEX-R2.txt
    M llvm/test/MC/Disassembler/X86/x86-64-err.txt

  Log Message:
  -----------
  [X86][MC] Support decoding of EGPR for APX (#72102)

https://github.com/llvm/llvm-project/pull/70958 adds registers R16-R31
(EGPR), this patch


1. Supports decoding of EGPR for instruction w/ REX2 prefix
2. Supports decoding of EGPR for instruction w/ EVEX prefix

For simplicity's sake,  we 
1.  Simulate the REX prefix w/ the 1st payload of REX2
2.  Simulate the REX2 prefix w/ the 2nd and 3rd payloads of EVEX

RFC:

https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4

Explanations for some changes:
1. invalid-EVEX-R2.txt is deleted b/c `0x62 0xe1 0xff 0x08 0x79 0xc0` is
valid and decoded to `vcvtsd2usi %xmm0, %r16` now.
2. One line in x86-64-err.txt is removed b/c APX relaxes the limitation
of the 1st and 2nd payloads of EVEX prefix, so the error message changes