[all-commits] [llvm/llvm-project] 223836: [AArch64] Prevent v1f16 vselect/setcc type expansi...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2238363a5f3081274b54dd0d1b0ff297e6940ba5
      https://github.com/llvm/llvm-project/commit/2238363a5f3081274b54dd0d1b0ff297e6940ba5
  Author: David Green <david.green at arm.com>
  Date:   2023-11-13 (Mon, 13 Nov 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/arm64-neon-v1i1-setcc.ll

  Log Message:
  -----------
  [AArch64] Prevent v1f16 vselect/setcc type expansion. (#72048)

PR #71614 identified an issue in the lowering of v1f16 vector compares,
where the `v1i1 setcc` is expanded to `v1i16 setcc`, and the `v1i16
setcc` tries to be expanded to a `v2i16 setcc` which fails. For floating
point types we can let them scalarize instead though, generating a
`setcc f16` that can be lowered using normal fp16 lowering.

07a8ff4892b2a54f0bd5843f863bcffa7a258f1f added a special case combine
for v1 vselect to expand the predicate type to the same size as the fcmp
operands. This turns that off for float types, allowing them to
scalarize naturally, which hopefully fixes the issue by preventing the
v1i16 setcc, meaning it wont try to widen to larger vectors.

The codegen might not be optimal, but as far as I can tell everything
generated successfully, providing that no `v1i16 setcc v1f16`
instructions get generated.