[all-commits] [llvm/llvm-project] 8c53cf: [RISCV][GISel] Rename register bank tablegen recor...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8c53cfd351a963118e18a47ffd5175308fb108f8
      https://github.com/llvm/llvm-project/commit/8c53cfd351a963118e18a47ffd5175308fb108f8
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-11 (Sat, 11 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBanks.td

  Log Message:
  -----------
  [RISCV][GISel] Rename register bank tablegen records to include B suffix to match the MIR name. NFC

GPRRegBank -> GPRBRegBank
FPRRegBank -> FPRBRegBank