[all-commits] [llvm/llvm-project] fdc904: [RISCV] Add isel pattern to turn (or (zext X), Y) ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fdc904e5681c00f5e347f5889f4dfd4a448ebaf4
      https://github.com/llvm/llvm-project/commit/fdc904e5681c00f5e347f5889f4dfd4a448ebaf4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-11 (Sat, 11 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll

  Log Message:
  -----------
  [RISCV] Add isel pattern to turn (or (zext X), Y) into add.uw when X and Y are disjoint.

Improve code for -riscv-experimental-rv64-legal-i32.