[all-commits] [llvm/llvm-project] 994d88: [RISCV] Add an slli.uw pattern using zext for -ris...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 994d882e151c07498ee47bff09f58724113ed87c
      https://github.com/llvm/llvm-project/commit/994d882e151c07498ee47bff09f58724113ed87c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-11 (Sat, 11 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVGISel.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zba.ll

  Log Message:
  -----------
  [RISCV] Add an slli.uw pattern using zext for -riscv-experimental-rv64-legal-i32

We already had the pattern for GlobalISel. Move it over to SelectionDAG.