[all-commits] [llvm/llvm-project] 2f8e3d: [lldb][AArch64][Linux] Add field information for t...

[David Spickett via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2f8e3d55da68b08f63186fa9f98245145a180449
      https://github.com/llvm/llvm-project/commit/2f8e3d55da68b08f63186fa9f98245145a180449
  Author: David Spickett <david.spickett at linaro.org>
  Date:   2023-11-10 (Fri, 10 Nov 2023)

  Changed paths:
    M lldb/packages/Python/lldbsuite/test/lldbtest.py
    M lldb/source/Plugins/Process/Utility/RegisterFlagsLinux_arm64.cpp
    M lldb/source/Plugins/Process/Utility/RegisterFlagsLinux_arm64.h
    M lldb/test/API/commands/register/register/aarch64_mte_ctrl_register/TestMTECtrlRegister.py
    M lldb/test/API/linux/aarch64/mte_core_file/TestAArch64LinuxMTEMemoryTagCoreFile.py

  Log Message:
  -----------
  [lldb][AArch64][Linux] Add field information for the mte_ctrl register (#71808)

This is a Linux pseudo register provided by the NT_ARM_TAGGED_ADDR_CTRL
register set. It reflects the value passed to prctl
PR_SET_TAGGED_ADDR_CTRL.

https://docs.kernel.org/arch/arm64/memory-tagging-extension.html

The fields are made from the #defines the kernel provides for setting
the value. Its contents are constant so no runtime detection is needed
(once we've decided we have this register in the first place).

The permitted generated tags is technically a bitfield but at this time
we don't have a way to mark a field as preferring hex formatting.

```
(lldb) register read mte_ctrl
mte_ctrl = 0x000000000007fffb
         = (TAGS = 65535, TCF_ASYNC = 0, TCF_SYNC = 1, TAGGED_ADDR_ENABLE = 1)
```

(4 bit tags mean 16 possible tags, 16 bit bitfield)

Testing has been added to TestMTECtrlRegister.py, which needed a more
granular way to check for XML support, so I've added hasXMLSupport that
can be used within a test case instead of skipping whole tests if XML
isn't supported.

Same for the core file tests.