[all-commits] [llvm/llvm-project] 679cc1: [RISCV] Disable early promotion for Zbs in perform...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 679cc16c99c74c485233febb8d5b77ec4a8f0290
      https://github.com/llvm/llvm-project/commit/679cc16c99c74c485233febb8d5b77ec4a8f0290
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-09 (Thu, 09 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbs.ll

  Log Message:
  -----------
  [RISCV] Disable early promotion for Zbs in performANDCombine with riscv-experimental-rv64-legal-i32

We can match this directly in isel with the i32 type being legal.

The generic DAG combine will unpromote part of the pattern and
prevent it from being matched in isel.