[all-commits] [llvm/llvm-project] 7ac848: [RISCVInsertVSETVLI] Allow PRE with non-immediate ...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7ac8486e54d99ed72c15da391dbeed134a37bae5
      https://github.com/llvm/llvm-project/commit/7ac8486e54d99ed72c15da391dbeed134a37bae5
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2023-11-09 (Thu, 09 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
    M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll

  Log Message:
  -----------
  [RISCVInsertVSETVLI] Allow PRE with non-immediate AVLs (#71728)

Extend our PRE logic to cover non-immediate AVL values. This covers
large constant AVLs (which must be materialized in registers), and may
help some code written explicitly with intrinsics.

Looking at the existing code, I can't entirely figure out why I thought
we needed VL == AVL to perform the PRE. My best guess is that I was
worried about the VLMAX < VL < 2 * VLMAX case, but the spec explicitly
says that vsetvli must be determinist on any particular AVL value.

That case was, possibly by accident, covering another legality
precondition. Specifically, by only returning true for immediate and
VLMAX AVL values, we didn't encounter the case where the AVL was a
register and that register wasn't available in the predecessor (e.g. if
AVL is a load in the MBB block itself).

---------

Co-authored-by: Luke Lau <luke_lau at icloud.com>