[all-commits] [llvm/llvm-project] c9017b: [X86] Support EGPR (R16-R31) for APX (#70958)

[Shengchen Kan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c9017bc79397e12734b58165273ae70f328d0002
      https://github.com/llvm/llvm-project/commit/c9017bc79397e12734b58165273ae70f328d0002
  Author: Shengchen Kan <shengchen.kan at intel.com>
  Date:   2023-11-09 (Thu, 09 Nov 2023)

  Changed paths:
    M llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
    M llvm/lib/Target/X86/X86.td
    M llvm/lib/Target/X86/X86InstrInfo.cpp
    M llvm/lib/Target/X86/X86InstrInfo.h
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.td
    M llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
    A llvm/test/CodeGen/X86/apx/mul-i1024.ll
    A llvm/test/CodeGen/X86/apx/no-rex2-general.ll
    A llvm/test/CodeGen/X86/apx/no-rex2-pseudo-amx.ll
    A llvm/test/CodeGen/X86/apx/no-rex2-pseudo-x87.ll
    A llvm/test/CodeGen/X86/apx/no-rex2-special.ll
    M llvm/test/CodeGen/X86/ipra-reg-usage.ll
    M llvm/test/CodeGen/X86/musttail-varargs.ll
    M llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
    M llvm/test/MC/AsmParser/seh-directive-errors.s
    A llvm/test/MC/X86/apx/cfi-reg.s

  Log Message:
  -----------
  [X86] Support EGPR (R16-R31) for APX (#70958)

1. Map R16-R31 to DWARF registers 130-145.
2. Make R16-R31 caller-saved registers.
3. Make R16-31 allocatable only when feature EGPR is supported
4. Make R16-31 availabe for instructions in legacy maps 0/1 and EVEX
space, except XSAVE*/XRSTOR

RFC:

https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4

Explanations for some seemingly unrelated changes:

inline-asm-registers.mir, statepoint-invoke-ra-enter-at-end.mir:
The immediate (TargetInstrInfo.cpp:1612) used for the regdef/reguse is
the encoding for the register
  class in the enum generated by tablegen. This encoding will change
  any time a new register class is added. Since the number is part
  of the input, this means it can become stale.

seh-directive-errors.s:
   R16-R31 makes ".seh_pushreg 17" legal

musttail-varargs.ll:
It seems some LLVM passes use the number of registers rather the number
of allocatable registers as heuristic.

This PR is to reland #67702 after #70222 in order to reduce some
compile-time regression when EGPR is not used.