[all-commits] [llvm/llvm-project] 3f9d38: [AArch64][SME] Shuffle lowering, assume that the m...

[Dinar Temirbulatov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3f9d385e5844f2f1f144305037cfc904789c6187
      https://github.com/llvm/llvm-project/commit/3f9d385e5844f2f1f144305037cfc904789c6187
  Author: Dinar Temirbulatov <Dinar.Temirbulatov at arm.com>
  Date:   2023-11-08 (Wed, 08 Nov 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-vector-shuffle.ll

  Log Message:
  -----------
  [AArch64][SME] Shuffle lowering, assume that the minimal SVE register is 128-bit, when NOEN is not available. (#71647)

We can assume that the minimal SVE register is 128-bit, when NEON is not
available. And we can lower the shuffle shuffle operation with one
operand to TBL1 SVE instruction.