[all-commits] [llvm/llvm-project] 867ece: [RISCV] Add processor definition for XiangShan-Nan...

[Yingwei Zheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 867ece181afe59aa020d365928169d2ebdc7d74a
      https://github.com/llvm/llvm-project/commit/867ece181afe59aa020d365928169d2ebdc7d74a
  Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
  Date:   2023-11-08 (Wed, 08 Nov 2023)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note.c
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add processor definition for XiangShan-NanHu (#70294)

This PR adds the processor definition for XiangShan-NanHu, an
open-source high-performance RISC-V processor.

According to the official
[documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch/),
NanHu core supports
`RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval`.
I found that NanHu also supports `zicbom` and `zicboz`. You can find
them in the [source
code](https://github.com/OpenXiangShan/XiangShan/blob/5931ace35325a644a12f8ea27830a2de7489e7e7/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala#L426-L436).
Features supported by NanHu have been confirmed by @poemonsense.

---------

Co-authored-by: SForeKeeper <zkliu6 at gmail.com>