[all-commits] [llvm/llvm-project] 9e50c6: Revert "Reapply "RegisterCoalescer: Add implicit-d...

[Mitch Phillips via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9e50c6e6b5741895f58f3e530004052844b6af9f
      https://github.com/llvm/llvm-project/commit/9e50c6e6b5741895f58f3e530004052844b6af9f
  Author: Mitch Phillips <mitchp at google.com>
  Date:   2023-11-07 (Tue, 07 Nov 2023)

  Changed paths:
    M llvm/lib/CodeGen/RegisterCoalescer.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
    R llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
    R llvm/test/CodeGen/X86/coalescing-subreg-to-reg-requires-subrange-update.mir
    R llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir

  Log Message:
  -----------
  Revert "Reapply "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG""

This reverts commit ba385ae210b3659bc9dfb78ef1d280d03c2c3b5a.

Reason: Broke the MSan buildbot. See comments on
https://github.com/llvm/llvm-project/commit/ba385ae210b3659bc9dfb78ef1d280d03c2c3b5a
for more information.


  Commit: 9b2439167d9f794e317fecbdbb0a6e96f9ea4b56
      https://github.com/llvm/llvm-project/commit/9b2439167d9f794e317fecbdbb0a6e96f9ea4b56
  Author: Mitch Phillips <mitchp at google.com>
  Date:   2023-11-07 (Tue, 07 Nov 2023)

  Changed paths:
    M llvm/test/CodeGen/X86/coalescer-implicit-def-regression-imp-operand-assert.mir

  Log Message:
  -----------
  Revert "RegisterCoalescer: Generate test checks"

This reverts commit 9832eb4bdd92e876a59fea5a3502572dc9bcf870.

Reason: Dependency on change that was reverted in
https://github.com/llvm/llvm-project/commit/ba385ae210b3659bc9dfb78ef1d280d03c2c3b5a


Compare: https://github.com/llvm/llvm-project/compare/48f980c535ca...9b2439167d9f