[all-commits] [llvm/llvm-project] 8d24d3: [Mips] In LowerShift*Parts, xor with bits-1 instea...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8d24d3900ec3f28902b2fad4a2c2c2b789257424
      https://github.com/llvm/llvm-project/commit/8d24d3900ec3f28902b2fad4a2c2c2b789257424
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-03 (Fri, 03 Nov 2023)

  Changed paths:
    M llvm/lib/Target/Mips/MipsISelLowering.cpp
    M llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
    M llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
    M llvm/test/CodeGen/Mips/llvm-ir/shl.ll

  Log Message:
  -----------
  [Mips] In LowerShift*Parts, xor with bits-1 instead of -1. (#71149)

If we start with an i128 shift, the initial shift amount would usually
have zeros in bit 8 and above. xoring the shift amount with -1 will set
those upper bits to 1. If DAGCombiner is able to prove those bits are
now 1, then the shift that uses the xor will be replaced with undef.
Which we don't want.

Reduce the xor constant to VT.bits-1 where VT is half the size of the
larger shift type. This avoids toggling the upper bits. The hardware
shift instruction only uses the lower bits of the shift amount. I assume
the code used NOT because the hardware doesn't use the upper bits, but
that isn't compatible with the LLVM poison semantics.

Fixes #71142.