[all-commits] [llvm/llvm-project] 17970d: [LLVM][SVE] Move ADDVL isel patterns under UseScal...

[Paul Walker via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 17970df6dca3cf46f0264e94f40eb4ef93ef521f
      https://github.com/llvm/llvm-project/commit/17970df6dca3cf46f0264e94f40eb4ef93ef521f
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2023-11-03 (Fri, 03 Nov 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll
    M llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll
    M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
    M llvm/test/CodeGen/AArch64/sve-gep.ll
    M llvm/test/CodeGen/AArch64/sve-insert-element.ll
    M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
    M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll
    M llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll
    M llvm/test/CodeGen/AArch64/sve-vl-arith.ll

  Log Message:
  -----------
  [LLVM][SVE] Move ADDVL isel patterns under UseScalarIncVL feature flag. (#71173)

Also removes a duplicate pattern.