[all-commits] [llvm/llvm-project] 014390: [RISCV] Implement cross basic block VXRM write ins...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 014390d9377ffa7c02a27eae7dca3b4e5967aeb6
      https://github.com/llvm/llvm-project/commit/014390d9377ffa7c02a27eae7dca3b4e5967aeb6
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-11-02 (Thu, 02 Nov 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/CMakeLists.txt
    M llvm/lib/Target/RISCV/RISCV.h
    M llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
    A llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O0-pipeline.ll
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    A llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll

  Log Message:
  -----------
  [RISCV] Implement cross basic block VXRM write insertion. (#70382)

This adds a new pass to insert VXRM writes for vector instructions. With
the goal of avoiding redundant writes.

The pass does 2 dataflow algorithms. The first is a forward data flow to
calculate where a VXRM value is available. The second is a backwards
dataflow to determine where a VXRM value is anticipated.

Finally, we use the results of these two dataflows to insert VXRM writes
where a value is anticipated, but not available.

The pass does not split critical edges so we aren't always able to
eliminate all redundancy.

The pass will only insert vxrm writes on paths that always require it.