[all-commits] [llvm/llvm-project] 860f9e: [NFC][X86] Reorder the registers to reduce unneces...

[Shengchen Kan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 860f9e5170767c08a879b592c9121d35e90a320e
      https://github.com/llvm/llvm-project/commit/860f9e5170767c08a879b592c9121d35e90a320e
  Author: Shengchen Kan <shengchen.kan at intel.com>
  Date:   2023-11-02 (Thu, 02 Nov 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/LiveVariables.h
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/include/llvm/TableGen/Record.h
    M llvm/include/llvm/Target/Target.td
    M llvm/lib/CodeGen/LiveVariables.cpp
    M llvm/lib/Target/X86/AsmParser/X86Operand.h
    M llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
    M llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.h
    M llvm/lib/Target/X86/X86RegisterInfo.td
    M llvm/test/CodeGen/X86/ipra-reg-usage.ll
    M llvm/utils/TableGen/CodeGenRegisters.cpp

  Log Message:
  -----------
  [NFC][X86] Reorder the registers to reduce unnecessary iterations (#70222)

* Introduce field `PositionOrder` for class `Register` and
`RegisterTuples`
* If register A's `PositionOrder` < register B's `PositionOrder`, then A
is placed before B in the enum in X86GenRegisterInfo.inc
* The new order of registers in the enum for X86 will be
      1. Registers before AVX512,
      2. AVX512 registers (X/YMM16-31, ZMM0-31, K registers)
      3. AMX registers (TMM)
      4.  APX registers (R16-R31)
* Add a new target hook `getNumSupportedRegs()` to return the number of
registers for the function (may overestimate).
* Replace `getNumRegs()` with `getNumSupportedRegs()` in LiveVariables
to eliminate iterations on unsupported registers

This patch can reduce 0.3% instruction count regression for sqlite3
during compile-stage (O3) by not iterating on APX registers
for #67702