[all-commits] [llvm/llvm-project] 2efea5: [AArch64] Fix spilling/filling of virtual register...

[Sander de Smalen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2efea512c25bb6f6178e0ff881a96e99b2aecee4
      https://github.com/llvm/llvm-project/commit/2efea512c25bb6f6178e0ff881a96e99b2aecee4
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2023-11-01 (Wed, 01 Nov 2023)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
    M llvm/test/CodeGen/AArch64/spillfill-sve.mir

  Log Message:
  -----------
  [AArch64] Fix spilling/filling of virtual registers in PNR regclass. (#70679)

We made the assumption that the registers were always physical
registers, which doesn't have to be true.