[all-commits] [llvm/llvm-project] 093bc6: [RISCV] SiFive7 VLDS Sched should not depend on VL...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 093bc6b61a6c87e138a4bf89fe620f6e63d20eda
      https://github.com/llvm/llvm-project/commit/093bc6b61a6c87e138a4bf89fe620f6e63d20eda
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-10-30 (Mon, 30 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVScheduleV.td
    A llvm/test/tools/llvm-mca/RISCV/SiFive7/strided-load-x0.s

  Log Message:
  -----------
  [RISCV] SiFive7 VLDS Sched should not depend on VL when stride is x0. (#70266)

When stride is x0, a strided load should behave like a unit stride load,
which uses the VLDE sched class.

---------

Co-authored-by: Wang Pengcheng <wangpengcheng.pp at bytedance.com>