[all-commits] [llvm/llvm-project] fe8335: [AMDGPU] Select 64-bit imm moves if can be encoded...

[Stanislav Mekhanoshin via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fe8335babba1725e18d6ea94073c3dbb92958bfa
      https://github.com/llvm/llvm-project/commit/fe8335babba1725e18d6ea94073c3dbb92958bfa
  Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
  Date:   2023-10-30 (Mon, 30 Oct 2023)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
    M llvm/lib/Target/AMDGPU/SIInstructions.td
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global-saddr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memmove.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memset.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll
    M llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers.ll
    M llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
    M llvm/test/CodeGen/AMDGPU/combine_andor_with_cmps.ll
    M llvm/test/CodeGen/AMDGPU/commute-compares.ll
    M llvm/test/CodeGen/AMDGPU/constrained-shift.ll
    M llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
    M llvm/test/CodeGen/AMDGPU/fold-int-pow2-with-fmul-or-fdiv.ll
    M llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll
    M llvm/test/CodeGen/AMDGPU/fract-match.ll
    M llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
    M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
    M llvm/test/CodeGen/AMDGPU/inline-asm.ll
    M llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
    M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
    M llvm/test/CodeGen/AMDGPU/ipra-return-address-save-restore.ll
    M llvm/test/CodeGen/AMDGPU/lds-atomic-fmin-fmax.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.w64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w32.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.w64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll
    M llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
    M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
    M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
    M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
    M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
    M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
    M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
    M llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
    M llvm/test/CodeGen/AMDGPU/sdiv64.ll
    M llvm/test/CodeGen/AMDGPU/shl.ll
    M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
    M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
    M llvm/test/CodeGen/AMDGPU/srem64.ll
    M llvm/test/CodeGen/AMDGPU/swdev380865.ll
    M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
    M llvm/test/CodeGen/AMDGPU/udiv64.ll
    M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
    M llvm/test/CodeGen/AMDGPU/urem64.ll
    M llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
    M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll

  Log Message:
  -----------
  [AMDGPU] Select 64-bit imm moves if can be encoded as 32 bit operand (#70395)

This allows folding of 64-bit operands if fit into 32-bit. Fixes
https://github.com/llvm/llvm-project/issues/67781