[all-commits] [llvm/llvm-project] 05b518: [Clang][RISCV] Support CSRs in clobbered registers...

[Wang Pengcheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 05b5188c1257785c4138834b81ec86047517376d
      https://github.com/llvm/llvm-project/commit/05b5188c1257785c4138834b81ec86047517376d
  Author: Wang Pengcheng <137158460+wangpc-pp at users.noreply.github.com>
  Date:   2023-10-23 (Mon, 23 Oct 2023)

  Changed paths:
    M clang/lib/Basic/Targets/RISCV.cpp
    A clang/test/CodeGen/RISCV/riscv-inline-asm-clobber.c

  Log Message:
  -----------
  [Clang][RISCV] Support CSRs in clobbered registers of inline assembly (#67646)

To match GCC's behaviors.

Fixes #67596