[all-commits] [llvm/llvm-project] 972709: [RISCV][GISel] Minor refactoring of RISCVCallRetur...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 972709a74a0c47998e1caeca888673a761dae9ca
      https://github.com/llvm/llvm-project/commit/972709a74a0c47998e1caeca888673a761dae9ca
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2023-10-20 (Fri, 20 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp

  Log Message:
  -----------
  [RISCV][GISel] Minor refactoring of RISCVCallReturnHandler and RISCVIncomingValueHandler to match other targets (#69757)

Forward assignValueToReg to the base class to make the copy. Add
markPhysRegUsed to contain the differences between call handling and
argument handling. Introduce RISCVFormalArgHandler.

This structure matches how AArch64, AMDGPU, and X86 are structured.

I've also added `MIRBuilder.getMRI()->addLiveIn(PhysReg);` to match the
other targets.