[all-commits] [llvm/llvm-project] dbc1b7: [RISCV][llvm-mca] Vector Unit Stride Loads and sto...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: dbc1b71cf454d75d5f5265d2d1d2b2273c03d22a
      https://github.com/llvm/llvm-project/commit/dbc1b71cf454d75d5f5265d2d1d2b2273c03d22a
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2023-10-20 (Fri, 20 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
    A llvm/test/tools/llvm-mca/RISCV/vle-vse.s

  Log Message:
  -----------
  [RISCV][llvm-mca] Vector Unit Stride Loads and stores use EEW and EMU… (#69409)

…L based on instruction EEW

Vector Unit Stride Loads and stores EEW and EMUL depend on the EEW given
in the instruction name and the SEW from vtype. llvm-mca needs some help to correctly report
this information.