[all-commits] [llvm/llvm-project] e353cd: [RISCV] Apply `IsSignExtendingOpW = 1` on `fcvtmod...

[Min-Yih Hsu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e353cd8173db939af22a6fd90705e35fbadb01a7
      https://github.com/llvm/llvm-project/commit/e353cd8173db939af22a6fd90705e35fbadb01a7
  Author: Min-Yih Hsu <min.hsu at sifive.com>
  Date:   2023-10-19 (Thu, 19 Oct 2023)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
    A llvm/test/CodeGen/RISCV/opt-w-instrs.mir

  Log Message:
  -----------
  [RISCV] Apply `IsSignExtendingOpW = 1` on `fcvtmod.w.d` (#69633)

Such that RISCVOptWInstrs can eliminate the redundant sign extend.