[all-commits] [llvm/llvm-project] b1a6b2: [AArch64][GlobalISel] Fix miscompile on carry-in s...

[Tobias Stadler via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b1a6b2cc409e5d54080638ee2df5d8fea698dee2
      https://github.com/llvm/llvm-project/commit/b1a6b2cc409e5d54080638ee2df5d8fea698dee2
  Author: Tobias Stadler <mail at stadler-tobias.de>
  Date:   2023-10-19 (Thu, 19 Oct 2023)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/select-sadde.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ssube.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-uadde.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-usube.mir

  Log Message:
  -----------
  [AArch64][GlobalISel] Fix miscompile on carry-in selection (#68840)

Eliding the vReg to NZCV conversion instruction for G_UADDE/... is illegal if
it causes the carry generating instruction to become dead because ISel
will just remove the dead instruction.
I accidentally introduced this here: https://reviews.llvm.org/D153164.
As far as I can tell, this is not exposed on the default clang settings,
because on O0 there is always a G_AND between boolean defs and uses, so
the optimization doesn't apply. Thus, when I tried to commit
https://reviews.llvm.org/D159140, which removes these G_ANDs on O0, I
broke some UBSan tests.
We fix this by recursively selecting the previous (NZCV-setting) instruction before continuing selection for the current instruction.